Difference between revisions of "74ALS175"
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Numberformat (talk | contribs) (Created page with "== FEATURES == * Four edge-triggered D flip-flops * Buffered common clock * Buffered asynchronous master reset * True and complementary outputs == DESCRIPTION == The 74ALS175...") |
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| − | = | + | = Quad D flip-flop 74ALS175 = |
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The 74ALS175 is a quad, edge-triggered D-type flip-flops with | The 74ALS175 is a quad, edge-triggered D-type flip-flops with | ||
individual D inputs and both Q and Q outputs. The common buffered | individual D inputs and both Q and Q outputs. The common buffered | ||
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applications where both true and complement outputs are required, | applications where both true and complement outputs are required, | ||
and the clock and master reset are common to all storage elements. | and the clock and master reset are common to all storage elements. | ||
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| + | [[http://pdf.datasheetcatalog.com/datasheet/philips/74ALS175D.pdf datasheet]] | ||
Latest revision as of 15:48, 26 June 2021
Quad D flip-flop 74ALS175
The 74ALS175 is a quad, edge-triggered D-type flip-flops with individual D inputs and both Q and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and complement outputs are required, and the clock and master reset are common to all storage elements.