Difference between revisions of "Xi8088 Version 2.0"
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When the processor starts up it will be looking at fixed memory location 0xFFFF0 for the jump instruction that will tell the processor the location of the POST Entry Point typically this number will be (EA 5B E0 00 F0). EA is the machine code for JMP FAR absolute 4 byte address specified in the argument. The F000:E05B is the address to jump to. Scrolling up in the window you will see that there is some BIOS code that starts at that point this is the POST entry point which starts with a B8 which is a MOV instruction. | When the processor starts up it will be looking at fixed memory location 0xFFFF0 for the jump instruction that will tell the processor the location of the POST Entry Point typically this number will be (EA 5B E0 00 F0). EA is the machine code for JMP FAR absolute 4 byte address specified in the argument. The F000:E05B is the address to jump to. Scrolling up in the window you will see that there is some BIOS code that starts at that point this is the POST entry point which starts with a B8 which is a MOV instruction. | ||
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== Troubleshooting == | == Troubleshooting == | ||
Revision as of 19:13, 7 July 2021
Introduction
Xi 8088 IBM PC/XT compatible processor board. The information on this page is specific for the integrated circuit kit I sell online. Most information could be used at your own risk if you are sourcing your own chips.
Contributions Welcome
If anyone reading this page is interested in contributing content please send me a text message at 3476042083 with your email address and I will send instructions on how to setup an account.
Features
- ISA board form factor
- Support of PS/2 keyboard and mouse
- Built-in real time clock with NVRAM
Board Layout
Click on any chip for more information. Most of the chips below lead to blank pages. I am looking for help in populating them with some info. I know datasheets are available however it would be nice to have a brief summary of each component and what is does overall on this board.
Post Assembly
Once you have your board assembled you can proceed with configuring the memory map. If you plan on using a VGA graphics card and the 128Kb BIOS Flash Chip then all the switches should be in the off position.
Memory Map
The 20 bit address bus of the 8088/86 allows 1 Mb of memory space with address range from 00000-FFFFF. During the design phase of the first IBM PC, engineers had to decide n the allocation of the 1-megabyte memory space to various sections of the PC. This memory allocation is called a memory map.
| Start Address | End Address | Size | Purpose | Comments | ||||||||||||||
| 0x00000h | 0x9FFFFh | 640 KiB | Base memory | |||||||||||||||
| 0xA0000h | 0xBFFFFh | 128 KiB | Display memory | |||||||||||||||
| 0xC0000h | 0xEFFFFh | 192 KiB | Upper memory blocks (UMB) and BIOS extension ROMs | Consists of six 32 KiB user configurable blocks, can be either mapped to SRAM (to be used as UMB) or used for BIOS extension ROMs
| ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0xE0000h | 0xEFFFFh | 64 KiB | On-board BIOS extension ROM | This is the upper 64 KiB of the 192 KiB block seen above. System flash ROM can be mapped here, so it can be used for BIOS extensions
| ||||||||||||||
| 0xF0000h | 0xFFFFFh | 64 KiB | System BIOS | Currently BIOS uses only top 32 KiB of this space (0xF8000h - 0xFFFFFh). The other 32 KiB part is mapped to the flash ROM and can be used for BIOS extensions
|
| Position | Description |
| 8 | ON = Monochrome display (MDA)
OFF = Color display (CGA) |
Burning the BIOS onto 39SF010 128k EEPROM chip
Use the 128k bios downloaded from the designer's website. Burn the bios128k-2.0.bin file starting from the beginning address space of the chip.
If you inspected the BIOS binary image you may be wondering why the upper half of the ROM chip's address range is empty. The reason for this is the design of the board internally flips the A16 address line that is going to the ROM chip using an logic inverter (U40 pin 3,4). To the processor the lower half of the ROM's address range (0x00000) appears at the upper half (0x10000).
The position of the SW2.7 does not affect the boot up. The ROM chip will always respond to the 0xFxxxx address range and if you have SW2.7 in the OFF position this chip will also be active for the 0xExxxx address range thus utilizing the now inverted 64Kb bottom address range of the chip for any custom BIOS extension code you decide to put there.
During product testing the TL866 II writer with the XGecu Pro software was used. These are available on eBay for pretty cheap.
Processor Bootstrap
When the processor starts up it will be looking at fixed memory location 0xFFFF0 for the jump instruction that will tell the processor the location of the POST Entry Point typically this number will be (EA 5B E0 00 F0). EA is the machine code for JMP FAR absolute 4 byte address specified in the argument. The F000:E05B is the address to jump to. Scrolling up in the window you will see that there is some BIOS code that starts at that point this is the POST entry point which starts with a B8 which is a MOV instruction.
Troubleshooting
Board layout and schematics are a must have reference. They are available at the designers website. The following section will try to address some of the common troubleshooting topics.
Does not boot
There could be many reasons why its not booting. This section will grow as I get more feedback from others.
- But for now I noticed a common issue is burning the boot ROM in the wrong byte offset on the chip. The A16 line is inverted so the top half of the 128kb ROM chip appears in the bottom half of the address space. See my notes about burning the BIOS to the ROM chip above.
- Use 2 510 ohm resistors for the clock instead of the 2 33pF caps.
- Other common issues include bad solder on pins.
No sound or continuous sound from speaker
To enable internal speaker connect a jumper across pins 1-2 of the speaker header pins. The speaker beeps a few times when performing the POST boot. If the speaker sounds continously then you may have received a active speaker instead of passive.
POST checkpoint codes (sent to port 80h during POST)
e_boot equ 00h ; Boot the OS e_start equ 01h ; BIOS POST started e_cpu_ok equ 02h ; CPU test passed e_dmac_ok equ 03h ; DMAC initialized e_low_ram_ok equ 04h ; low RAM test passed e_int_ok equ 05h ; interrupt table initialized e_pit_ok equ 06h ; PIT (timer) initialized e_pic_ok equ 08h ; PIC initialized e_kbd_ok equ 10h ; KBD test passed e_video_bios_ok equ 11h ; Video BIOS found e_video_init_ok equ 12h ; Video BIOS initialized e_rtc_init_ok equ 20h ; RTC initialized e_cpu_detect_ok equ 21h ; CPU type detected e_fpu_detect_ok equ 22h ; FPU type detected e_serial_ok equ 24h ; Serial port scan finished e_parallel_ok equ 25h ; Parallel port scan finished e_ram_start equ 30h ; RAM test start e_ram_complete equ 31h ; RAM test completed e_ram_esc equ 32h ; RAM test canceled e_ext_start equ 40h ; Start BIOS extension ROM scan e_ext_detect equ 41h ; BIOS extension ROM found e_ext_init_ok equ 42h ; BIOS extension ROM initialized e_ext_complete equ 43h ; BIOS extension scan complete e_cpu_fail equ 52h ; CPU test failed e_low_ram_fail equ 54h ; low RAM test failed e_kbd_ctrl_fail equ 60h ; KBD test - controller selftest failed e_kbd_key_fail equ 61h ; KBD test - echo test failed e_kbd_timeout equ 62h ; KBD timeout e_kbd_int_fail equ 63h ; KBD test - interface test failed e_ram_fail equ 80h ; RAM test failed