User contributions for Numberformat

Results for Numberformat talk block log uploads logs

A user with 581 edits. Account created on 5 May 2021.

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03:4303:43, 4 July 2021 diff hist 0 N File:Xi8088 enable internal speaker.jpg No edit summary current
03:3603:36, 4 July 2021 diff hist +399 Xi8088 Version 2.0 →Troubleshooting
03:3103:31, 4 July 2021 diff hist +2 Xi8088 Version 2.0 No edit summary
03:3103:31, 4 July 2021 diff hist +118 Xi8088 Version 2.0 →Troubleshooting
00:0900:09, 4 July 2021 diff hist +40 Xi8088 Version 2.0 →Processor Bootstrap
00:0800:08, 4 July 2021 diff hist 0 N File:Xi8088 post success.jpg No edit summary

22:2222:22, 3 July 2021 diff hist +678 Xi8088 Version 2.0 No edit summary
22:1522:15, 3 July 2021 diff hist −363 Xi8088 Version 2.0 →Processor Bootstrap

03:5903:59, 1 July 2021 diff hist +148 N 74ALS02 Created page with "== Quad 2-Input NOR gate == Outputs on pins 1, 4, 10, 13 https://pdf1.alldatasheet.com/datasheet-pdf/view/15231/PHILIPS/74ALS02.html datasheet" current
03:5603:56, 1 July 2021 diff hist +47 74F573 No edit summary current

20:4820:48, 26 June 2021 diff hist −165 74ALS175 No edit summary current
15:4915:49, 26 June 2021 diff hist +344 N 74F245 Created page with "= Octal Bidirectional Transceiver with 3-STATE Outputs = In the U18 board position this is used as a bi-directional transceiver for the 8 bit data bus. In the U19, 20, 21 po..." current
15:1515:15, 26 June 2021 diff hist +390 N 74F573 Created page with "Due to chip packaging limitations in the 1970s, there was great effort to use the minimum number of pins for external connections. Intel multiplexed address & data buses, usi..."

14:2214:22, 23 June 2021 diff hist +14 ISA Backplane →ISA Bus
14:2114:21, 23 June 2021 diff hist 0 N File:ISA Bus pins.png No edit summary current
03:3603:36, 23 June 2021 diff hist +120 N 8259 Created page with "= PROGRAMMABLE INTERRUPT CONTROLLER = https://pdf1.alldatasheet.com/datasheet-pdf/view/66107/INTEL/8259A.html link" current
03:3403:34, 23 June 2021 diff hist −39 8288 →The Intel 8288 is a bus controller designed for Intel 8086/8087/8088/8089 current
02:4802:48, 23 June 2021 diff hist +129 N 8288 Created page with "= The Intel 8288 is a bus controller designed for Intel 8086/8087/8088/8089 = https://en.wikipedia.org/wiki/Intel_8288 link"
01:5001:50, 23 June 2021 diff hist −24 ISA Backplane →POST Codes and what they mean
00:3400:34, 23 June 2021 diff hist +1,427 Xi8088 Version 2.0 →Troubleshooting

03:3403:34, 22 June 2021 diff hist −893 Xi8088 Version 2.0 No edit summary

22:3322:33, 20 June 2021 diff hist +1,086 Xi8088 Version 2.0 No edit summary
21:3321:33, 20 June 2021 diff hist +794 Xi8088 Version 2.0 →Processor Bootstrap
21:0221:02, 20 June 2021 diff hist −1 Xi8088 Version 2.0 →Processor Bootstrap
20:3120:31, 20 June 2021 diff hist +554 Xi8088 Version 2.0 No edit summary
19:5219:52, 20 June 2021 diff hist +25 Xi8088 Version 2.0 No edit summary
19:5019:50, 20 June 2021 diff hist +142 Xi8088 Version 2.0 No edit summary
18:4918:49, 20 June 2021 diff hist +1,936 Xi8088 Version 2.0 No edit summary
18:0918:09, 20 June 2021 diff hist +17 File:Ibm pc memory map.jpg No edit summary current
18:0318:03, 20 June 2021 diff hist 0 N File:Ibm pc memory map.jpg No edit summary

18:3918:39, 19 June 2021 diff hist +122 N 8284 Created page with "== Clock Generator for the 8088 == https://pdf1.alldatasheet.com/datasheet-pdf/view/124124/INTEL/8284A.html Datasheet" current
03:2603:26, 19 June 2021 diff hist +111 8254 No edit summary current
03:2403:24, 19 June 2021 diff hist +120 8254 No edit summary
03:1503:15, 19 June 2021 diff hist +86 8254 No edit summary
03:1203:12, 19 June 2021 diff hist +110 74ALS74 No edit summary current
03:0403:04, 19 June 2021 diff hist +121 N 74F244 Created page with "== Octal Buffer Line Driver == [https://pdf1.alldatasheet.com/datasheet-pdf/view/173145/FAIRCHILD/74F244.html Datasheet]" current
03:0003:00, 19 June 2021 diff hist +82 N 74ALS74 Created page with "[https://pdf1.alldatasheet.com/datasheet-pdf/view/27763/TI/74ALS74.html Datasheet]"
02:5402:54, 19 June 2021 diff hist +88 N 74ALS00 Created page with "[https://pdf1.alldatasheet.com/datasheet-pdf/view/15230/PHILIPS/74ALS00A.html Datasheet]" current
00:2800:28, 19 June 2021 diff hist +73 Xi8088 Version 2.0 →Non-Turbo clock is unstable or non existent
00:2700:27, 19 June 2021 diff hist +46 Xi8088 Version 2.0 →Proposed Improvements
00:2400:24, 19 June 2021 diff hist +452 N 8254 Created page with "The 82C54 is a programmable interval timer/counter. The 82C54 solves the problem of generation of accurate time delays under software control. Instead of setting up timing lo..."

23:1523:15, 18 June 2021 diff hist +221 ISA Backplane No edit summary
23:1323:13, 18 June 2021 diff hist +30 Xi8088 Version 2.0 No edit summary
23:1123:11, 18 June 2021 diff hist +102 Xi8088 Version 2.0 →Proposed Improvements
22:1722:17, 18 June 2021 diff hist −92 Xi8088 Version 2.0 →Proposed Improvements
21:5521:55, 18 June 2021 diff hist +243 Xi8088 Version 2.0 →Board Layout
21:5421:54, 18 June 2021 diff hist −2 Xi8088 Version 2.0 No edit summary
21:5321:53, 18 June 2021 diff hist +193 Xi8088 Version 2.0 No edit summary
21:4521:45, 18 June 2021 diff hist +387 Xi8088 Version 2.0 →Proposed Improvements
04:3804:38, 18 June 2021 diff hist +114 Xi8088 Version 2.0 →Proposed Improvements

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